Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today announced that Metanoia Communications, a ...

Partners empower systems engineers with best-in-class SysML v2 modeling Solutions; New Systems Modeler for SysML v2 Powered by IBM Rhapsody Systems Engineering f ...

June 2nd, 2025: T2MIP, The world’s largest independent global semiconductor IP cores provider, proudly announces the launch of its latest high-performance ADC IP core: a 12-bit SAR ADC capable of ...

June 2, 2025 -- We’re honoured to be named a runner-up in the Arm Flexible Access Startup Contest, announced during the Silicon Catalyst Portfolio Company Update event here in Silicon Valley.

Focus on the core product by ensuring the creation of differentiated, and essential chip technology that enables the critical systems of today and tomorrow – from smart phones to smart cars and homes, ...

“The global HPC race demands accelerators that deliver extreme performance per watt,” said Oliver Jones, CEO of Aion Silicon. “This project shows how our team can turn bold RISC-V architectures into ...

Imec CEO Luc Van den hove opened ITF World 2025 by calling for “disruptive innovation over incremental change”. He underscored the need for tighter global collaboration to overcome looming bottlenecks ...

Speaking at the recent RISC-V Summit Europe 2025 in Paris, Thomas Dombek, head of Digital Integrated Circuits and Systems Department at CEA, looked back on seven years of involvement in the RISC-V ...

Bridging the gap, however, is becoming a bigger challenge, said K. Charles Janac, the CEO of Arteris. "Effectively addressing hardware and software integration has become quite a challenge for SoC ...

At its 2025 Europe Technology Symposium in Amsterdam, The Netherlands, TSMC announced that it is establishing a European design center in Munich, scheduled to open in Q3 2025 in order to support its ...

Professor Kim Joung-ho of the Korea Advanced Institute of Science & Technology (KAIST), widely recognized as a leading expert in high-bandwidth memory (HBM) design, will present a 15-year roadmap for ...

Typically, SoCs now comprise between 5 to 20 individual NoC instances, occupying approximately 10-13% of the total silicon ...