TSMC held its North America Technology Symposium on Wednesday, April 23, 2025 at the Santa Clara Convention Center and ...

TL;DR: TSMC's advanced 2nm process node, featuring GAAFET architecture, matches 5nm defect density and surpasses 3nm and 7nm stages ... be using all-around gate transistor (GAAFET) architecture ...

TSMC's 2nm process node is cruising through development and is already showing better defect rates than 3nm and 7nm did at the same stage. According to Taiwanese outlet Ctee, the node now matches ...

This is in addition to offering advanced packaging technologies for client and AI/HPC applications ... in general, and TSMC in particular. Maximum transistor density and performance efficiency.

Additionally, transistor density ... TSMC started a special microchip miniaturization process, called 5nm FinFET technology, that played a crucial role in smartphone and high-performance computing ...

TSMC stated that its N2 fabrication technology got more new tape outs than predecessors (as TSMC now risks producing N2 chips for smartphone and HPC customers), so the defect density decrease ...

The increased transistor density alone, you would think ... Driven by AI accelerators as well as high performance CPUs and switch ASICs, the so-called HPC sector at TSMC (which is not restricted to ...

TSMC expects its N3 process to be a long-running and high volume node. At the company’s North American Technology Symposium, Kevin Zhang, TSMC’s SVP for Business Development and Overseas Operations ...

TSMC expects to implement its Super Power Rail technology for HPC applications at its N16 node in 2026 ... potentially affecting transistor characteristics. Using virtual fabrication, a recent study ...

IGMTLSX06A is a synchronous LVT / ULVT periphery high-density ternary content addressable memory (TCAM) with column redundancy feature. It is developed with TSMC 7nm 0.75V/1.8V CMOS LOGIC FinFET ...