TSMC had already provided low ... indicated that Intel 4 (back then called 7nm) would land somewhere between N5 and N3 with regards to transistor density. However, based on current information ...

TL;DR: TSMC's advanced 2nm process node, featuring GAAFET architecture, matches 5nm defect density and surpasses 3nm and 7nm stages ... be using all-around gate transistor (GAAFET) architecture ...

Why it matters: The cost of progress is getting steeper with each new manufacturing process TSMC develops ... of 10nm and 7nm with the A11 and A12. Those two chips saw transistor density hikes ...