The SiFive E31 Standard Core is the world's most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient ...
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Last week, OnChip released the RISC-V Open-V in real, tangible silicon. Choice is always a good thing, and now SiFive, a fabless semiconductor company, has released the HiFive1 as a crowdfunding ...
Powered by the Eswin EIC7700X SoC with a quad-core SiFive P550 CPU, it provides a robust platform for developing and optimizing RISC-V operating systems and applications across diverse markets. It ...
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This is the general hardware-specific BSP layer for the SiFive boards. But changes are also validated on Qemu RISC-V 64bits, so this layer also provide a Kas yaml to build this machine. Building disk ...
SAN FRANCISCO, April 2, 2018 --SiFive, the leading provider of commercial RISC-V processor IP, today announced it raised $50.6 million in a Series C round led by existing investors Sutter Hill ...
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