Last week, OnChip released the RISC-V Open-V in real, tangible silicon. Choice is always a good thing, and now SiFive, a fabless semiconductor company, has released the HiFive1 as a crowdfunding ...

The SiFive E31 Standard Core is the world's most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient ...

A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system ... The SiFive E31 Standard Core is the world's most deployed RISC-V core. Co-designed alongside the RISC ...

Powered by the Eswin EIC7700X SoC with a quad-core SiFive P550 CPU, it provides a robust platform for developing and optimizing RISC-V operating systems and applications across diverse markets. It ...

This is the general hardware-specific BSP layer for the SiFive boards. But changes are also validated on Qemu RISC-V 64bits, so this layer also provide a Kas yaml to build this machine. Building disk ...