China is ramping up its RISC-V ambitions with the launch of the Shanghai Open Source Computing Research Institute, unveiled at the 5th RISC-V Summit China on July 17, 2025. As the country's second ...

RISC-V, pronounced “Risk-five,” is especially inviting to startups because it’s an open technology, overseen by a consortium of tech firms.

It’s built for a RISC-V processor, since that instruction set is completely open source and transparent about what it’s doing. It’s also incredibly small, coming in at around 2000 lines of code.

Development Tools PolarFire Core devices are supported by Microchip’s Libero® SoC Design Suite, SmartHLS™ compiler, VectorBlox™ Accelerator SDK and Microchip’s Mi-V ecosystem of partner ...

Nearly half of global silicon projects now incorporate AI or machine learning (ML), spanning automotive, mobile, data center, and Internet of Things (IoT) applications. This rapid RISC-V evolution is ...

ECARX launched its RISC-V-based EXP01 processor and outlined its automotive-grade MCU roadmap at the RISC-V Summit Europe 2025.

In a keynote speech at the RISC-V Summit Europe 2025 in Paris, Emmanuel Till-Vattier, VP of sales EMEA at Codasip, presented a brief product update, including new possibilities for fast migration from ...

RISC-V is a proposal from Vitalik Buterin that aims to rethink the Ethereum execution layer. Learn about the proposal and how it might solve the scalability conundrum.

RISC-V enhances the competitiveness of U.S. chip design firms by creating a flexible, low-risk, and low-cost platform for collaboration. To capitalize on this opportunity, the United States should ...

Discover how RISC-V is transforming computing in 2025, from embedded systems to data centers, with open innovation and global adoption.