With the steady progress, RISC-V could soon be powering some of the powerful devices in the future. More importantly, the RISC-V chipsets can even be run on as many cores as the x86 and ARM ...

A new technical paper titled “Bendable non-silicon RISC-V microprocessor” was published by researchers at Pragmatic Semiconductor, Qamcom, and Harvard University. From the abstract: “Here we present ...

The shift from Arm to RISC-V microprocessor cores marks a significant change for Qualcomm and a huge design win for the RISC-V architecture.

It now has a gang (generally called the RISC-V community or ecosystem) ... The MIPS eVocore P8700 microprocessor core is a deeply pipelined, out-of-order (OOO), multi-threaded, ...

Back in early 2023, Google announced that it was working on enabling support for the RISC-V architecture in Android. RISC-V is an open instruction set architecture that’s grown in popularity in ...

A team of engineers at Fudan University has successfully designed, built and run a 32-bit RISC-V microprocessor that uses molybdenum disulfide instead of silicon as its semiconductor component.

Today Nature journal publishes Pragmatic Semiconductor’s latest research article, a Bendable Non-silicon RISC-V Microprocessor, demonstrating the world’s first 32-bit microprocessor in a flexible ...

Founded in 2015, RISC-V produces low-cost, efficient, and flexible architecture that can be customised to specific use cases. Crucially, it’s also open source, which means no single entity ...

The newly minted chipmaking startup AheadComputing Inc. said today it has raised $21.5 million in seed funding to develop and commercialize a new artificial intelligence chipset based on the open ...

A new technical paper titled “RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures” was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and ...

If you read Japanese, you might have seen the book “Design and Implementation of Microkernels” by [Seiya Nuda]. An appendix covers how to write your own operating system for RISC-V in a… ...