SiFive, the gold standard for RISC-V, today announced a collaboration with Red Hat, the world’s leading provider of enterprise open source solutions, to bring Red Hat Enterprise Linux support to ...

Developer preview of Red Hat Enterprise Linux 10 on SiFive HiFive Premier P550 platform provides developers with a platform to optimize a new class of enterprise and cloud computing applications ...

SiFive, the gold standard for RISC-V, today announced a collaboration with Red Hat, the world’s leading provider of enterprise open source solutions, to bring Red Hat Enterprise Linux support to the ...

SiFive's Coreplex IP has demonstrated significantly better power efficiency compared to other, competing ISAs. Two initial Coreplex design configurations are available at launch: E31 Coreplex ? The ...

today announced the availability of Lauterbach's TRACE32 toolset to provide debug capabilities for SiFive's E31 and E51 RISC-V Core IP, based on the free and open RISC-V ISA. Lauterbach support for ...

gem5 is an open-source simulator that supports many architectures, including RISC-V, and organizations such as AMD, ARM, Google, Intel, Qualcomm and SiFive use it for research, development, and ...

Copyright: © 2025 World Health Organization; licensee Elsevier Ltd. We evaluated the effects of digital health technologies (DHTs) on women's health, empowerment ...

SiFive has partnered with Kinara to create a USB-based enablement board that provides access to the SiFive Intelligence X280 processor and sample code. Bare metal access to RISC-V Vector processors ...

The board itself uses ESWIN’s advanced RISC-V AI SoC EIC7702X—sorry for even more caps, it’s how it’s stylised—which is a 64-bit RISC-V processor with 8 SiFive P550 ‘out-of-order’ CPU cores. What is ...