The U5 core has a 5-6 stage pipeline and supports virtual memory, enabling ... The SiFive E31 Standard Core is the world's most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 ...

The SiFive E31 Standard Core is the world's most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient ...

Last week, OnChip released the RISC-V Open-V in real, tangible silicon. Choice is always a good thing, and now SiFive, a fabless semiconductor company, has released the HiFive1 as a crowdfunding ...

Powered by the Eswin EIC7700X SoC with a quad-core SiFive P550 CPU, it provides a robust platform for developing and optimizing RISC-V operating systems and applications across diverse markets. It ...

The original version of Kami was developed in MIT. Based on the experience of developing and using Kami at MIT, it was rewritten at SiFive to make it practical to build provably correct chips. While ...

After hours: March 14 at 6:08:02 PM EDT Loading Chart for CEVA ...

This branch holds all platforms actively maintained against the edk2 master branch. For generic information about the edk2-platforms repository, and the process under which stable and devel branches ...