GCRAM combines the density advantages of embedded DRAM with SRAM performance, ... The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32 ...
40LP High density dual port SRAM compiler with Vss booster feature This DDR PHY IP(Double Data Rate) supports DRAM type DDR3, DDR3L this PHY provides low latency, and enables up to 1600Mbps throughput ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results
Feedback