Electronic Design

DFT Compiler/ATPG Tool Combo Aids In DFT

The integration of DFT Compiler in the physical compiler environment facilitates design-for-test (DFT) closure. According to the manufacturer, this addition enables fast timing closure with fully ...
Design-Reuse

Using in-design physical verification to reduce tapeout schedules

. Tadahiko Yamamoto is Chief Specialist, Design Methodology Development Group, at Toshiba Corp. . Norikazu Ooishi is Specialist, Design Methodology Group, at Toshiba Corp. Physical designers moving to ...
Electronic Design

Design Compiler Points Toward Better Physical Implementation

Synopsys' Design Compiler 2010 accounts for the challenges of modern physical IC design, offering floor plan exploration from within the synthesis environment. It also delivers physical guidance to IC ...
Semiconductor Engineering

Advanced Design Planning In IC Compiler II

Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has been architected ...
Design-Reuse

TASKING presents compiler toolset for RISC-V in safety- and security-critical automotive applications

The new VX-Toolset for RISC-V meets the requirements of ISO 26262 and ISO/SAE 21434. Munich, Germany, April 9, 2024 – TASKING introduces the new compiler toolset VX-Toolset for RISC-V. The industry's ...
EDN

Synopsys IC Compiler II Sets the Bar in Quality-of-Results

Technology developments in latest release cement IC Compiler II's QoR leadership by delivering 5 percent better area, 5 percent better timing QoR and up to 20 percent reduction in power. With 19 of ...
Business Wire

Silvaco Acquires Memory Compiler Technology of Dolphin Design SAS

SANTA CLARA, Calif.--(BUSINESS WIRE)--Silvaco Inc., a leading supplier of EDA software and design IP, today announced that it has completed the acquisition of the memory compiler technology and ...