The test chip, fabricated in 90 nm CMOS technology, occupied a core area of ${0.04}\;{{\text{m}}{\text{m}}^{2}}$. With a 0.4 V supply and a Nyquist rate input, the prototype consumed 200 nW at 250 ...

The design occupies 6 mm 2 in 28-nm CMOS, contains 328 kB of on-chip SRAM, operates at 237 frames/s (FPS), and consumes 0.9 mW from 0.6 V/0.8 V supplies. The corresponding energy per classification (3 ...