EDN

JEDEC begins to draft standard for advanced DDR-III SDRAM chips

Future-generation DDR-III SDRAM surfaced here last week at the JEDEX chip conference, flaunting performance levels twice as good as DDR-II. The JEDEC Solid State Technology Association, the ...
EDN

JEDEC discloses DRAM roadmap, but 400-MHz DDR may not make the cut

SANTA CLARA, Calif. — During the first-ever JEDEX conference today, a representative from JEDEC outlined a roadmap for the “mainstream” DRAM market, disclosing that his organization “may or may not” ...
Yahoo Finance

JEDEC Announces Annual Update of DDR5 Serial Presence Detect (SPD) Contents Standard

ARLINGTON, Va., October 14, 2025--(BUSINESS WIRE)--JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, has published the annual ...
Hexus

JEDEC releases final specification for DDR5 SDRAM

JEDEC, the Solid State Technology Association, has announced the final DDR5 SDRAM specification. This new standard promises to deliver doubled memory bandwidth, alongside support for quadruple density ...

Adata & MSI Unveil 4-Rank DDR5 Modules For Massive Memory Capacities

DDR5 memory runs objectively high transfer rates; JEDEC specs go as high as 6.4 Gbps, and overclockers have taken DDR5 beyond the fastest LPDDR5X: all the way to over 13 Gbps. At these speeds, signal ...
Odessa American

JEDEC Publishes DDR4 NVDIMM-P Bus Protocol Standard

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD304-4.01 DDR4 NVDIMM-P Bus Protocol. The ...
Business Wire

JEDEC Publishes Update to DDR5 SDRAM Standard Used in High-Performance Computing Applications

ARLINGTON, Va.--(BUSINESS WIRE)--JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced publication of the JESD79-5A ...
Design-Reuse

Altera Announces Industry's First Full-Compliance With New JEDEC DDR3 SDRAM Standard

Stratix III FPGAs are the First and Only FPGAs Supporting 1.5V Low-Power DDR3 Memory, Yielding 30% System Power Reduction San Jose, July 16, 2006 —Altera Corporation (NASDAQ: ALTR) today announced ...
Electronic Design

Eye-Diagram Analysis Speeds DDR SDRAM Validation

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...
Electronic Design

DDR Bus Simulator to solve BER contour simulation challenge

September 30, 2014. Keysight Technologies today introduced the DDR Bus Simulator—the industry’s first tool to generate accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification ...
Business Wire

JEDEC Publishes DDR4 NVDIMM-P Bus Protocol Standard

ARLINGTON, Va.--(BUSINESS WIRE)--JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD304-4.01 ...