This paper focuses on the production testing of Memristor Ratioed Logic (MRL) XOR gate. MRL is a family that uses memristors along with CMOS inverters to design logic gates. The two-input MRL XOR gate ...

LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by ...

This repository contains the design and implementation of a 4-bit Mealy Machine-based Overlapping Sequence Detector for detecting the sequence "1001" using 90nm CMOS technology and simulated in ...