For those unaware, ARM and x86 are two types of microprocessor architecture or Instruction Set Architecture (ISA). ISA is the first step of a CPU design, whether it’s RISC-V, x86, or ARM.

A new technical paper titled “Bendable non-silicon RISC-V microprocessor” was published by researchers at Pragmatic Semiconductor, Qamcom, and Harvard University. From the abstract: “Here we present ...

RISC-V is an open-source architecture that is gaining increased popularity in the hardware space, and Google has been steadily working on implementing support for it in Android.

A team of engineers at Fudan University has successfully designed, built and run a 32-bit RISC-V microprocessor that uses molybdenum disulfide instead of silicon as its semiconductor component ...

The result was a RISC processor the team calls the Flex-RV. The demonstration chips thus far have a core size of 17.5 square millimeters and 12,600 logic gates, which limits their speed to 60 kHz.

Calista Redmond, chief executive of the microprocessor consortium RISC-V International, is a fan of the wild days of chip competition back in the 1980s. "This is the biggest opportunity to change ...

Google and Qualcomm partner to bring the RISC-V microprocessor architecture to wearables Qualcomm Today, Google and Qualcomm announced an extension of their partnership to bring RISC-V-based ...

The advantage for MIPS is that it’s no longer fighting its perennial foe, Arm, all by itself. It now has a gang (generally called the RISC-V community or ecosystem) helping in the fight through ...

A new technical paper titled “RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures” was published by researchers at Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and ...

Intel and RISC-V working together is a game-changer, and today is the day that RISC-V becomes a chip power. Written by Steven Vaughan-Nichols, Senior Contributing Editor Feb. 7, 2022 at 2:13 p.m. PT ...