The newly minted chipmaking startup AheadComputing Inc. said today it has raised $21.5 million in seed funding to develop and commercialize a new artificial intelligence chipset based on the open ...

AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension. It ...

Chinese scientists have developed the world’s most complex two-dimensional (2D) semiconductor microprocessor, with the chip set to enter pilot-scale production. Details of the chip, which is ...

It supports RISC-V standard “G (IMA-FD)”, “C” 16-bit compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector) extensions, and Andes performance enhancements, plus Andes Custom Extension™ ...

A team of engineers at Fudan University has successfully designed, built and run a 32-bit RISC-V microprocessor that uses molybdenum disulfide instead of silicon as its semiconductor component.

According to Tom's Hardware, unlike GPUs from AMD, Intel, and Nvidia that rely on proprietary instruction set architectures, Bolt's Zeus relies on the open-source RISC-V ISA, according to the ...

The C930 will begin shipping to clients this month, according to Damo, without providing figures, at a the chip’s launch on February 28 in Beijing. Its CPU design is available for licensing to ...

An appendix covers how to write your own operating system for RISC-V in about 1,000 lines of code. Don’t speak Japanese? An English version is available free on the Web and on GitHub.