Agilex 7 FPGA M-Series features a hardened memory Network-on-Chip (NoC) interface that delivers the industry’s highest memory bandwidth, up to 1 TBps, using in-package HBM2E and hardened DDR5 ...

which meets the increasingly higher memory bandwidth needs of SoCs targeted for the next generation of AI training and HPC hardware systems. The Cadence HBM4 solution is compatible with the JEDEC ...

The design is validated in hardware using the most recently available MRDIMMs (Gen2), achieving a best-in-class 12.8Gbps data rate that doubles the bandwidth using current DDR5 6400Mbps DRAM parts.

Apple is reportedly planning to equip the 2026 models with a high-capacity six-channel LPDDR5X memory configuration, significantly upping the memory bandwidth for future AI features and multitasking.