Design-Reuse19d
A 55-nm Ultra Low Leakage SRAM Compiler with Optimized Power Gating Design
Lots of methods have been discussed on power gating design. In [1], SRB method is used. In sleep mode footer NMOS is cut off and in retention mode GND is bounced ηVt. It needs DC/DC converter to ...
Design-Reuse2y
Low Power High Density Clock Gate
This paper presents a low power Clock Gating scheme for clock power improvement that reduces ... as EN cannot make a 0-1 transition during CP high. Also by adding two new NMOS for feedback for ...