PORTLAND, Ore.--(BUSINESS WIRE)--Oct. 3, 2001--Model Technology(TM), a Mentor Graphics company, today announced that the ModelSim® hardware description language (HDL) simulator has received Verilog ...

PORTLAND, Ore.--Nov. 28, 2000--Xilinx, Inc. and Model Technology, a Mentor Graphics company, today announced that the Intellectual Property (IP) Solutions Division of Xilinx has standardized on ...

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...

Aiming to bring advanced verification languages like SystemVerilog and advanced methods like assertion-based verification to mainstream IC designers, Mentor Graphics this week is introducing its new ...

Wilsonville, Ore.-based Model Technology, a Mentor Graphics company, today releases ModelSim 5.5, a new version of its HDL simulation tool to be used for multimillion gate ASIC and FPGA designs.

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...

The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.