In traditional CMOS technology, metal-semiconductor (MS) contact schemes, with transition-metal silicides (such as nickel (Ni) silicides) on the metal side, are used to form the source/drain contacts.

Researchers have found a way to make the chip design and manufacturing process much easier — by tapping into a hybrid blend ...

Due to the improved contact interface, 2D semiconductor transistors fabricated using this technique exhibited more than 95% reduction in off-state current and a 50% decrease in subthreshold swing ...

Coplanar semiconductor–metal circuitry defined on few-layer MoTe2 via polymorphic heteroepitaxy. Nature Nanotechnology, 2017; DOI: 10.1038/NNANO.2017.161 ...

At its core, computing relies on manipulating electric currents and fields. But as devices shrink to the nanometer scale, controlling these flows becomes increasingly difficult. Wires and transistors ...

In a paper recently published in the open-access journal ACS Applied Energy Materials, researchers studied the usage of polymeric films of polyethylenimine (PEI) for interfacial enhancement of ...

[1] Amorphous oxide semiconductor contact resistance Researchers from the Tokyo Institute of Technology and National Institute for Materials Science developed a way to reduce contact resistance in ...

Charge transport in hybrid silicon solar cells Date: August 17, 2015 Source: Helmholtz-Zentrum Berlin für Materialien und Energie Summary: A surprising discovery has been made about hybrid ...