According to new information, the Tensor G2 is, in fact, built upon a 5nm manufacturing process and ... elements such as clock speed and core layout somewhat tarnished by incorrect die size ...

layout, using hybrid copper bonding (HCB). Fujitsu is using the SRAM tiles (essentially huge caches) are made on TSMC's N5 process node, with the compute and cache stacks loaded with a huge I/O ...