AMD wants to patent a new DDR5 memory standard with double the bandwidth but we're not expecting to see it in PCs any time soon

A n AMD patent application for a new spin on DDR5 PC memory has been spotted. The so-called high-bandwidth dual inline memory ...
EDN

JEDEC begins to draft standard for advanced DDR-III SDRAM chips

Future-generation DDR-III SDRAM surfaced here last week at the JEDEX chip conference, flaunting performance levels twice as good as DDR-II. The JEDEC Solid State Technology Association, the ...
EDN

JEDEC describes new DDR-II specs, says first parts due out in late 2002

SANTA CLARA, Calif. — During the JEDEX conference here, representatives from the DRAM and PC industries outlined some of the first public details and specifications for a second-generation, ...
Odessa American

JEDEC Publishes DDR4 NVDIMM-P Bus Protocol Standard

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD304-4.01 DDR4 NVDIMM-P Bus Protocol. The ...
Design-Reuse

Altera Announces Industry's First Full-Compliance With New JEDEC DDR3 SDRAM Standard

Stratix III FPGAs are the First and Only FPGAs Supporting 1.5V Low-Power DDR3 Memory, Yielding 30% System Power Reduction San Jose, July 16, 2006 —Altera Corporation (NASDAQ: ALTR) today announced ...
The Register on MSN

Ruh-roh. DDR5 memory vulnerable to new Rowhammer attack

Google and ETH Zurich found problems with AMD/SK Hynix combo, will probe other hardware Researchers from Google and Swiss ...
Business Wire

JEDEC Publishes Update to DDR5 SDRAM Standard Used in High-Performance Computing Applications

ARLINGTON, Va.--(BUSINESS WIRE)--JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced publication of the JESD79-5A ...
Electronic Design

DDR Bus Simulator to solve BER contour simulation challenge

September 30, 2014. Keysight Technologies today introduced the DDR Bus Simulator—the industry’s first tool to generate accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification ...
Ars Technica

ATI goes DDR-II, and not wanting to go it alone

While NVIDIA fans wonder about the NV30's final configuration details, ATI claims to have "demonstrated" a 3D processor that's G'd up with DDR-II RAM. The development is interesting because the rumor ...
Business Wire

JEDEC Recognizes Nantero’s Bill Gervasi with Award of Excellence

ARLINGTON, Va.--(BUSINESS WIRE)--JEDEC Solid State Technology Association announced today that Bill Gervasi, Principal Systems Architect, Nantero, has been presented with the JEDEC Award of Excellence ...