Design-Reuse7y
Context Based Clock Gating Technique For Low Power Designs of IoT Applications - A DesignWare IP Case Study
In addition to the techniques discussed, system can be made low power by considering – Low Power RTL design, gate level optimization, frequency islands, power gating, multi supply voltage, multiple ...
Design-Reuse7y
Achieving Low power with Active Clock Gating for IoT in IPs
[3] Keating, Michael, et al. “Low power methodology manual: for system-on-chip design.” Springer Publishing Company, Incorporated, 2007. [4] G. Pouiklis et al., "Clock Gating Methodologies and Tools: ...