In its third major and field-programmable gate array (FPGA) announcement in the last 12 months, Lattice Semiconductor Corp. has introduced MachXO, a new product family that combines the key features ...
Altium has expanded support for system-level FPGA and CPLD development by adding a JTAG interface to its Nexar system. The addition of the JTAG port enables engineers to use their FPGA-development ...
Over on the University of Reddit there’s a course for learning all about FPGAs and CPLDs. It’s just an introduction to digital logic, but with a teacher capable of building a CPLD motor control board ...
HILLSBORO, OR - August 30, 2005 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that RAD Data Communications has selected the LatticeECâ„¢ FPGA as well as the ispMACHâ„¢ 4000 CPLD ...
Adding to the CoolRunner-II CPLD family, the XC2C32A and XC2C64A debut in smaller MLF packages than their predecessors and integrate an additional I/O bank to support voltage level translation and ...
These programmable-logic devices combine CPLD flash configurability with an FPGA lookup-table architecture for lower-cost, logic-intensive designs. Applications traditionally supported by high-density ...
[PK] is working on a very simple video card, meant to output 640×480 VGA with a cheap CPLD. The interface will be 5 Volt SPI, meaning there’s a ton of potential here for anyone wanting put a ...
SUNNYVALE, Calif.--Dec. 29, 2005--Synplicity, Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced the company grew its worldwide FPGA ...
A CPLD with on-chip phase locked loops, high speed I/O and extra wide logic functions has been introduced by Lattice. The ispMACH5000VG is aimed at bridging between communications interfaces and ...
Intel refreshed its FPGA line-up with cost-optimized offerings, released its FPGA software stack as open source, and added a new processor design based on the RISC-V architecture. The first of the new ...